`include "defines.v"

module if_id (
    input wire              clk,
    input wire              rst,

    input wire              stall_i,
    input wire              flush_i,

    input wire [63: 0]      inst_addr_i,
    input wire [31: 0]      inst_i,

    output reg [63: 0]      inst_addr_o,
    output reg [31: 0]      inst_o
);

    always @(posedge clk) begin
        if(rst == 1'b1 || flush_i == 1'b1)
        begin
            inst_addr_o <= `ZERO_WORD;
            inst_o      <= 32'h0;
        end
        else if(stall_i == 1'b1)
        begin
            inst_addr_o <= inst_addr_o;
            inst_o      <= inst_o;
        end
        else
        begin
            inst_addr_o <= inst_addr_i;
            inst_o      <= inst_i;
        end
    end
endmodule
